TAP interface card (TIC) Type 022 / SR NIGPIB

TAP interface card as a fixture module, used to connect interchangeable or permanently installed TEM or TEM/ISO

With the rapid development of network technology in the information age, the network provides people with more and more information. At the same time, as the scale of the network continues to expand, the data traffic carried by the network continues to increase sharply. Realizing real-time and efficient collection of high-speed network data streams is an important issue in network monitoring and network security. The data acquisition card system needs the host server as the carrier to obtain the data stream in the high-speed network in real time. After high-speed processing, it needs to transmit the large-flow and high-speed data stream to the host server. The development of high-speed IO bus technology makes it possible to develop this high-performance data acquisition system. The PCI Express bus is a third-generation high-performance IO bus developed on the basis of the traditional bus. It has the characteristics of high speed, high reliability, low cost and strong scalability. Both large servers and microcomputer systems have good support for PCI Express. Among all the current hardware systems that need to interact through the computer IO bus, the PCI Express bus has become the first choice for most systems to achieve high-speed transmission. On the basis of the related technical investigation and research of high-speed data acquisition system, we deeply understand and analyze the key technical points of the PCI Express bus architecture and implementation, and combine the functional requirements of the system and the performance requirements to be achieved. A design scheme of a high-speed data acquisition system based on PCI Express bus. The whole system includes two parts: hardware logic design and software drive. This article mainly explains the design and implementation of the system from the aspect of system hardware logic. Modularization is adopted in the development of system hardware logic, and the whole system is divided into three parts: Gigabit Ethernet access, data matching filtering and PCI Express bus DMA transmission to design and implementNIGPIB